The present invention relates generally to static random access memory (SRAM) cell, and, more particularly, to dual port SRAM cells.
Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. DRAM memory cell has only one transistor and one capacitor, so it provides a high degree of integration. But DRAM requires constant refreshing, its power consumption and slow speed limit its use mainly for computer main memories. SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as an adequate power is supplied. SRAM can operate at a higher speed and lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of a SRAM cell is a six transistor (6T) cell that comprises six metal-oxide-semiconductor (MOS) transistors. Briefly, a 6T SRAM cell 100, as shown in FIG. 1, comprises two identical cross-coupled inverters 102 and 104 that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between a power and a ground. Each inverter 102 or 104 comprises a NMOS pull-down transistor 115 or 125 and a PMOS pull-up transistor 110 or 120. The inverter's outputs serve as two storage nodes C and D, when one is pulled to low voltage, the other is pulled to high voltage. A complementary bit-line pair 150 and 155 is coupled to the pair of storage nodes C and D via a pair of pass-gate transistors 130 and 135, respectively. The gates of the pass-gate transistors 130 and 135 are commonly connected to a word-line 140. When the word-line voltage is switched to a system high voltage, or Vcc, the pass-gate transistors 130 and 135 are turned on to allow the storage nodes C and D to be accessible by the bit-line pair 150 and 155, respectively. When the word-line voltage is switched to a system low voltage, or Vss, the pass-gate transistors 130 and 135 are turned off and the storage nodes C and D are essentially isolated from the bit lines, although some leakage can occur. Nevertheless, as long as Vcc is maintained above a threshold, the state of the storage nodes C and D is maintained indefinitely.
However, the traditional SRAM cell 100 has leakage current caused by both gate and off-state leakages. Assuming nodes C and D are at logic 0 and 1, respectively, in a static state, the pull-up transistor 110 and the pull-down transistor 125 contribute off-state leakages I_off_PU and I_off_PD, respectively, while the pull-up transistor 120 and the pull-down transistor 115 contribute gate leakages I_gate_PU and I_gate_PD, respectively. The pass-gate transistor 130 also contributes an off-state leakage, I_off_PG. Besides, the pass-gate transistor 135 contributes additional gate leakage, I_gate_PG. Therefore, a total leakage current, Isb, of the traditional SRAM cell 100 can be expressed as: Isb=(I_off_PU+I_off_PD+I_gate_PU+I_gate_PD)+I_off_PG+I_gate_PG. In more advanced process technologies, such as 80 nm and under, especially for high speed applications, thin gate oxide and shallow junction may make the leakage current in the traditional SRAM cell 100 unacceptable. Then the traditional SRAM cell 100 has only limited applications in the more advanced
Various techniques have been proposed to reduce the SRAM cell leakage current. For example, lowering power supply voltage to stand-by cells may reduce leakage current thereof. But operating SRAM array on multiple supply voltages increases design complexity and may also lowers the SRAM speed. Another example is to provide a virtual ground to each row of SRAM cells. With the boosted ground voltage, the SRAM cell leakage can also be reduced. But by using word-lines to control the rows of the virtual ground, this technique may also suffer slowed cell operation.
As such, what is desired is a SRAM cell that not only has suppressed leakage current, but also does not sacrifice operation speed.